The Synchronous Digital Hierarchy(called "SDH" thereinafter) of ITU-T relates to a transfer mode in a synchronous transfer network and has a Synchronous Transfer Module 1 (called "STM1" thereinafter) having a format of 9.times.270 as a basic transfer unit. As such kind of transfer frame is transmitted 8000 frames every second, STM1 has a transfer rate of 155.52 Mbps. The STM1 has a Section Overhead(called "SOH" thereinafter, SOH.dbd.RSOH+MSOH) for operation and management onto a transfer line within its frame, and may contain one Virtual Container 4 (called "VC4" thereinafter) having a format of 9.times.261 in the unit except for the SOH or three Virtual Containers 3 (called "VC3" thereinafter) having a format of 9.times.90. These Virtual Containers may begin at a given position of payload portion on a frame and represent the beginning position of VC on the frame as one pointer of overhead on the frame. The pointer indicates the beginning position of VC as the offset from a pointer byte, and the pointer value may vary based on the processing delay at a transfer apparatus and the difference between the clock rates when one VC passes through various transfer apparatus. Though there exist three pointers for three VC3 in STM1 frame, the first pointer is used when only one VC4 is conveyed and the other two are Concatenation Indication(called "CI" thereinafter).
"Concatenation" means that any VC is concatenated to a forehand VC to be a single VC having a larger capacity. This concatenated VC is processed as one unit until it is terminated without being divided in the interim. The first row at the VC4 having a format of 9.times.261 is used to transmit a Path Overhead (called "POH" thereinafter) which is used for Operation and Maintenance (called "OAM" thereinafter) associated with a convey of VC4. The remaining 9.times.260 portions represent the portions for conveying real data and are called a Container 4 (called "C4 " thereinafter). The C4 has a format of 9.times.260, which has a convey capacity of 149.76 Mbps.
In addition, VC4-4c is consisted of VC having a single convey capacity in which four VC4s are included therein, and can convey C4-4c in which four C4s are included therein. This VC4-4c can be conveyed by STM4 having a format in which four STM1s are interleaved at a byte unit. In this case, as the STM4 can convey one VC4-4c, only one pointer among 12 pointers is used and the remaining 11 pointers are represented as CI.
FIG. 1 is a schematic drawing to illustrate a synchronous transfer module(STM4-4c) and the operation thereof will explained as follows by reference to Table 1.
In Table 1 is shown a format of SOH and pointer when VC4-4cis conveyed onto STM4.
The sum of VC4-4c and pointers H1 and H2 indicating a beginning position of VC4-4c is called AU4-4c. When ATM cell is contained within the VC4-4c, a continuous flow of ATM cells is contained. As the beginning location of the ATM cells within a C4-4c is not fixed, the ATM cells may be positioned over the boundary of the VC4-4c. Any prior technologies relating to a method for implementing a ATM cell physical layer circuit for a Synchronous Optical Network (called "SONET" thereinafter)/STM are not known.
TABLE 1 __________________________________________________________________________ A1 A1 A1 . . . A1 A2 A2 A2 . . . A2 J0 C1 C1 C1 . . . B1 . . . E1 . . . F1 . . . D1 . . . D2 . . . 1* D3 . . . H1 Y Y . . . Y H2 1* 1* . . . 0 0 0 0 0 . . . 0 B2 . . . . . . . . . D4 . . . D5 . . . D6 . . . D7 . . . D8 . . . D9 . . . D10 . . . D11 . . . D12 . . . S1 . . . M1 . . . . . . 12 COLUMN 12 COLUMN 12 COLUMN __________________________________________________________________________
When using an improper structure to implement this kind of 622 Mbps ATM cell physical layer circuit, there is a drawback that implementing the circuit is difficult since the circuit operating rate of many units is as high as 77.76 MHz and the hardwares become complicated. In addition, as most functions are performed in a frame unit in view of STM circuit, when implemented by a Very Large Scale Integrated Circuit ("VLSI") such as Application-Specific Integrated Circuit("ASIC") etc., lots of time is required to verify most functions in a simulation during a design. Also, when testing a chip after processing, there is a drawback that the operation may not be tested in a real-like situation because too many number of vectors (the number of clocks) are needed to test the real-like operation with a test vector.